The present invention relates to a semiconductor memory device. More particularly, the present invention relates to a circuit for controlling a column selection line in a semiconductor memory device.
In semiconductor memory devices, and dynamic random access memories (DRAMs) in particular, as the level of integration increases, internal signal lines become longer, and their load increases accordingly. When the load of column address lines, which are internal signal lines, greatly increases, the operation speed of the device may slow down or current consumption may increase.
FIG. 1 is a block diagram schematically illustrating a conventional DRAM. Referring to FIG. 1, the conventional DRAM includes an address buffer 11, a column address decoder 12, a column selection line control signal generator 15, and a column selection line driver 13, and a memory cell array 14.
The address buffer 11 buffers externally-applied addresses A.sub.0 through A.sub.13 and provides column addresses CA.sub.0 through CA.sub.9, CA.sub.12, and CA.sub.13. The column address decoder 12 receives the column addresses CA.sub.0 through CA.sub.9, CA,.sub.12, and CA.sub.13, and decodes them into first and second decoded column addresses FDCA.sub.i and SDCA.sub.i. The column selection line control signal generator 15 receives the column addresses CA.sub.12 and CA.sub.13 and generates a column selection line control signal CSC in response to an internal clock signal ICLK. The column selection line driver 13 receives the first and second decoded addresses FDCA.sub.i and SDCA.sub.i (where i is an integer) of the column address decoder 12 and drives column selection lines CSL.sub.i (where, i is an integer) in response to the column selection line control signal CSC. These column selection lines CSL.sub.i are then provided to the memory cell array 14.
CA.sub.12 and CA.sub.13 denote bank selection bits when the memory cell array 14 includes a plurality of banks. The first decoded column address FDCA.sub.i denotes signals obtained by decoding CA.sub.0 through CA.sub.2 in the column address decoder 12, and the second decoded column address SDCA.sub.i denotes signals obtained by decoding CA.sub.3 through CA.sub.9 in the column address decoder 12.
FIG. 2 is a circuit diagram of a unit circuit in the column selection line driver 13 shown in FIG. 1. FIG. 3 is a circuit diagram of the column selection line control signal generator 15 shown in FIG. 1. FIG. 4 is a timing diagram of the signals shown in FIG. 2.
As described above, as the level of integration increases in a DRAM, the column address lines, which transmit the outputs of the address buffer 11, i.e., the buffered column addresses CA.sub.0 through CA.sub.9, CA.sub.12, and CA.sub.13, may be more greatly loaded. In addition, the loads of the column address lines may differ from one another.
For example, one of CA.sub.i (where i ranges from 0 to 9) may be delayed for a time t.sub.1 with respect to CA.sub.12 and CA.sub.13 as shown in FIG. 4. This may happen because of the difference between the loads of the column address lines. FIG. 4 shows a case in which one among CA.sub.3 through CA.sub.9 is delayed for a period of t.sub.1.
Accordingly, in the conventional DRAM, one among the second decoded column addresses SDCA.sub.i, which are generated by CA.sub.3 through CA.sub.9, i.e., SDCA.sub.j, has invalid data as indicated by the area a for a period of t.sub.1. Thus, one among the column selection lines CSL.sub.i, i.e., CSL.sub.x, is abnormally enabled in advance as indicated by the area b. As a result of this, two column selection lines are enabled simultaneously, which causes the DRAM to malfunction.